Clock frequency requirements of electronics systems are continually increasing. Thus, system designers must address increasingly complex clock synchronization requirements. For example, in a system which uses application specific integrated circuits (ASICs), it is important to minimize on-chip clock distribution delay and total system clock skew in order to provide for safe data transfer between the ASICs. The need for effective high frequency clock synchronization is therefore apparent.
Some conventional approaches to the problem of clock skew minimization provide a digital phase locked loop (PLL) for each IC in the system. Each PLL attempts to eliminate the effects of the on-chip clock distribution delay of the associated IC. Each PLL typically includes a phase detector and a digital delay line, each of which has the system clock as an input. The digital delay line is arranged as a component of the on-chip clock distribution path. The on-chip clock, obtained at the downstream end of the on-chip clock distribution path, is fed back as an input to the phase detector. The phase detector, typically a D flip-flop, detects information about the phase relationship between the system clock and the on-chip clock, and provides this information to the digital delay line. The digital delay line adjusts the delay of the on-chip clock distribution path based on the phase information provided by the phase detector. This feedback adjustment of the on-chip clock distribution path delay is continued until the on-chip clock and the system clock are acceptably synchronized.
Some conventional PLLs remove delay from the clock distribution path whenever the on-chip clock trails the system clock by less than one-half cycle, and add delay to the path whenever the on-chip clock trails the system clock by more than one-half cycle. However, upon initial start up, the delay path is typically at its minimum delay, and this minimum delay is often less than one-half cycle. Thus, the PLL will attempt to remove delay from the path, but the delay cannot decrease below its minimum value. As a result, the clocks cannot be synchronized.
Some conventional PLLs add delay even when the on-chip clock trails the system clock by less than one-half cycle. However, the conventional D flip-flop phase detector is not edge sensitive to rising edges only. Therefore, before the rising edge of the on-chip clock is delayed enough to reach the next rising edge of the system clock, it reaches the intervening falling edge of the system clock and is locked with this falling edge. Thus, the PLL will lock on either a falling edge or a rising edge of the system clock. This means that, for any given minimum delay time of the on-chip clock distribution path, the permissible frequency and duty cycle of the system clock are disadvantageously limited.
In order to avoid the aforementioned problems which can occur when the on-chip clock trails the system clock by less than one-half cycle, some systems have an external delay element provided in the system clock path upstream of the phase detector. The external delay element changes the phase relationship so that, at the phase detector input, the on-chip clock effectively trails the system clock by more than one-half cycle. That is, the external delay element forces the two clocks into a phase relationship which is more conducive to the PLL's synchronization capability. However, this solution disadvantageously introduces additional costs and design complexity.
Another problem with conventional PLLs is undesirably high phase jitter. Phase jitter is a function of the phase resolution of the phase detector and the step size of the digital delay line. Some conventional D flip-flop phase detectors have a phase resolution of about 400 ps. This alone can make the overall PLL phase jitter 500 ps or more.
In addition to the aforementioned phase detector problems, conventional PLLs are often operationally limited to a single frequency or a very narrow frequency range due to the structure of the digital delay line. One conventional delay line includes a plurality of serially connected delay elements, and a shift register which switches the delay elements to a longer or shorter delay to achieve lock. The clock signal propagates through each delay element. Another conventional delay line includes a plurality of serially connected delay elements, and a plurality of switches which couple the respective delay element outputs to the overall output of the delay line. By appropriate operation of the switches, a desired number of the delay elements can be selectively switched into or out of the clock path. Both of the aforementioned delay line structures limit the frequency range of the PLL. In addition, these approaches can introduce undesirable loading conditions which adversely affect the clock waveform.
In view of the foregoing discussion, it is desirable to provide a high performance digital PLL which overcomes the aforementioned problems associated with conventional PLLs.